Senior Digital Design Verification Engineer (SOC & IP)
My client - an world leading semiconductor company who manufacture a variety of cutting edge products - is looking to hire a Senior Digital Design Verification Engineer.
As Senior Digital Design verification Engineer you will be a leading engineer in the R & D team; responsible for hands-on verification duties, plus setting up, defining and developing existing and new processes..
The team is looking for a staff / senior Digital Design Verification Engineer to implement the UVM verification methodology, and execute the verification plan ensuring that their processors / SoCs deliver their industry-defining performance.
Engineers applying for this role MUST have - excellent knowledge of system verilog, C / C++ / system C AND UVM test benches*
The ideal candidate for this position will have :
- 10+ years' industry experience
- SoC design verification, SystemVerilog languages (UVM, SVA, SFC), low power verification (UPF methodology), software / hardware co-verification (System C / C / C++),
- Interfaced with designs / teams with embedded analog / mixed-signal design blocks,
- Track record of being a hands-on, involved engineering team player who delivered successful silicon SoCs with embedded processor cores and proven IP,
- Been comfortable interacting with customers, cross-domain teams,
- Enthusiasm to take ownership, contribute to realize innovative, landmark products and company.
Preferred skills for this role include :
- Embedded SoC development, processes, delivery,
- formal verification, jasper, SVA, assertions
- Proven in IP delivery, usage,
- Insight-fully hands-on with industry-standard EDA flows and methodologies,
- Digital design with VHDL, Verilog, System Verilog,
- Confident scripting experience - python, C, C++, system C, TcL
- automation processes - CI / CD,
- devops - git / github