Project engineer Jobs in Lausanne
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Project engineer • lausanne
Senior Photonic Design Engineer (ID : 2512)
Ligentec SALausanne, Kanton Waadt, CHMechanical Design Engineer
Swissels Engineering & Life Science ServicesLausanne, CH- Gesponsert
PROJECT MANAGER
Adecco Human Resources AGLausanne, CHProject Manager Engineering
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WSA Office ProjectCrissier, CHAssistant & Project Coordinator
IncyteMorges, Vaud, SwitzerlandSAP Project Manager (Finance & HR)
Michael PageVaud, CHData Engineer
Albedis LausanneLausanne, CHPROJECT MANAGER
LHHLausanne, Vaud, SwitzerlandSoftware Project Manager
microTECH Global LtdLausanne, SwitzerlandSenior Equipment Project Manager.
MedtronicTolochenaz, Vaud, SwitzerlandSenior IT Project Manager
Distalmotion SAÉpalinges, VD, CH- Gesponsert
Senoir Software Development Project Leader
WhatJobsEclépens, SchweizEmbedded Software Development Engineer
Sensile Technologies SAMorgesEmbedded Software Development Engineer
WIKA PolskaMorgesCryptographic Engineer
SICPAPrilly, CHElectromagnetic Engineer
H.GLASSEcublens, Lausanne, CHSenior Photonic Design Engineer (ID : 2512)
Ligentec SALausanne, Kanton Waadt, CHIntro LIGENTEC is a young, dynamic and strongly growing company, headquartered in Lausanne, Switzerland, near EPFL, close to the shore of Lake Geneva. We are developing Photonic Integrated Circuits (PICs) to world-leading performance with our customers for applications in Quantum Technologies, LiDAR, Space, Biosensors and more. To support our growth, we are looking for a : Senior Photonic Design Engineer (ID 2512) Tasks We are seeking a highly skilled and experienced Senior Design Engineer to join LIGENTEC’s engineering team. The ideal candidate will have a proven track record in designing and developing complex photonic integrated circuits (PICs). This role involves leading design efforts for customer and internal projects, with a focus on single component optimization, circuit-level simulations, data analysis, and circuit layout. Key Responsibilities : Lead the design and layout of PICs for customer and strategic roadmap projects Develop and maintain LIGENTEC’s layout library to ensure adherence to best layout practices Contribute to the design of active components based on III-V and LNOI material Conduct industry-level circuit simulations and analyze large datasets Develop and implement custom models to enhance design capabilities Collaborate with cross-functional teams on process and testing to ensure successful project execution. Perform project feasibility analysis and contribute to project management Provide mentorship to junior engineers and contribute to the overall design team growth Provide concise and clear documentation and reporting Requirements MSc or PhD in photonics or related fields. Minimum of 7+ years hands-on experience in integrated optics design and layout in a top environment, preferably industrial Problem-solver with a solutions-oriented mindset and critical thinking abilities Adaptable and thrives in a dynamic environment with shifting priorities. Collaborative team player and independent self-starter, capable of achieving both individual and group objectives Excellent communication and reporting Working proficiency in English Proficiency in : Designing passive photonic components and circuits Python programming and code versioning Single components and large circuits layout. IPKISS layout tool knowledge is a plus Familiarity with : How PIC manufacturing affects design and layout : design-for-testability and design-for-manufacturability Active components design and heterogeneous integration Developing custom analytic and semi-analytic models Benefits A flexible and dynamic start-up work environment. Be a member of an international, diverse, customer-focused and highly motivated team. Personal responsibility in your job and the chance to grow with us Our passion to bring PICs to everyday life. Closing We look forward to receiving your full application using reference 2512, including 1) your CV, 2) a statement of interest (relating the position to your skills), and 3) grade or work certificates. Incomplete applications may not be considered.