Digital Design / Verification Engineer (RISC-V)

Exciting new position available with a cutting-edge semiconductor company, located in the Zurich area of Switzerland.

The ideal candidate will have a mixture of digital design and digital verification experience over the last 5+ years.

• Bachelor / Masters / PHD in Electronic Engineering or similar field
• ASIC / FPGA digital design knowledge of complex tape-out projects (verilog / VHDL)
• Detailed understanding of UVM environments and RTL coding in verilog / system verilog
• Must have good scripting skills too - python, matlab, system C / C++
• Additional "nice to have skills" include knowledge of the full digital design flow, from architecture to RTL-GDS2 physical design / implementation / synthesis.

Please contact Rob Husdon for more information.