Senior Principal Digital IC Design Engineer

ppOur client is a globally recognised semiconductor innovator at the forefront of intelligent power and sensing technologies. Their solutions enable advances in automotive, industrial automation, renewable energy, cloud infrastructure, and AI-driven applications. With a strong focus on innovation, sustainability, and engineering excellence, they develop cutting‑edge semiconductor technologies that power the world's most demanding electronic systems. /p pThey are seeking an experienced bSenior Principal Digital IC Design Engineer /b to play a key role in the architecture and development of advanced digital IP and embedded systems for next‑generation semiconductor products. /p h3Key Responsibilities /h3 ul liLead the architecture, specification, implementation, and optimisation of complex digital IP blocks and embedded systems. /li liDesign and develop digital control peripherals, MCU/DSP subsystems, and hardware accelerator IPs. /li liEvaluate and benchmark new architectures to ensure optimal performance, efficiency, and scalability. /li liDrive improvements in design methodologies, development processes, and engineering quality standards. /li liProvide technical leadership across projects while mentoring and supporting junior engineers. /li liCollaborate closely with cross‑functional product and integration teams to define system requirements and deliver robust semiconductor solutions. /li liEnsure designs meet quality, reliability, timing, and power objectives throughout the development lifecycle. /li liProduce high‑quality technical documentation to support design and product development activities. /li /ul h3Qualifications /h3 ul liMaster's or PhD in Electrical Engineering, Electronics Engineering, or a related discipline. /li li15+ years of experience in digital IC design within the semiconductor industry. /li liProven expertise designing digital IP, MCU/DSP architectures, or hardware accelerator solutions. /li liStrong RTL design experience using Verilog and/or SystemVerilog. /li liExperience leading technical projects or engineering teams. /li liStrong understanding of design quality processes, including DFMEA and controlled design release methodologies. /li liKnowledge of timing constraints (SDC), power intent (UPF), and digital design best practices. /li liExcellent technical documentation and communication skills in English. /li liEligibility to work in Switzerland. /li liComplete RTL‑to‑GDSII design flow, including synthesis, place route, static timing analysis, and power optimisation. /li liDigital signal processing architecture and implementation. /li liAdvanced verification methodologies such as UVM. /li liFrench language skills would be advantageous. /li /ul pApply now or send your CV in confidence to . /p pSuitable applicants will be contacted with further details regarding the company and opportunity. /p /p #J-18808-Ljbffr