StellenbeschreibungpAt TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams. /ppReporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks. /ppbr / strongKey Responsibilities /strongbr /br / strongBlock-Level Execution Convergence Engineering (90%) /strong /pullipstrongEnd-to-End Testbench Ownership: /strongDesign, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units). /p /lilipstrongDatapath Arithmetic Verification: /strong Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units. /p /lilipstrongProof Convergence Management: /strong Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling). /p /lilipstrongRISC-V Vector Compliance: /strong Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification. /p /lilipstrongSimulation Partnership: /strong Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps. /p /li /ulpstrongEmbedded Mentorship Best Practices (10%) /strong /pullipstrongFormal-Friendly Design: /strong Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns. /p /lilipstrongSVA Propagation: /strongReview and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team. /p /li /ulpbr / /p br /br / ullipstrongEducation: /strong B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic. /p /lilipstrongExperience: /strong5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines. /p /lilipstrongCollaboration Style: /strong A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers. /p /lilipstrongDatapath Validation Focus: /strongStrong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome. /p /lilipstrongVector Microarchitecture: /strongGood working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus. /p /lilipstrongFormal Tools: /strong Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps. /p /lilipstrongLanguages: /strong Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation. /p /li /ul pstrongNice to Have /strong /pullipRISC-V Core Verification. /p /lilipstrongRISC-V Ecosystem: /strongFamiliarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems. /p /lilipEmulation platforms (Veloce, ZeBu). /p /lilipCore/Bus interface protocols (e.g., AXI/CHI). /p /li /ul
