Senior ASIC Physical Layout Engineer

pstrongSenior ASIC Physical Layout Engineer /strong /p p strong Location: Lausanne Area / Western Switzerland (Flexible working culture) /strong /p p strong Permanent Position /strong /p pAre you an experienced strongLayout Engineer /strong looking to work on strongcutting-edge mixed-signal ASICs /strong that push the boundaries of ultra-low-power technology? /p pI'm currently supporting a highly respected Swiss technology organisation in their search for a strongSenior ASIC Physical Layout Engineer /strong to join an experienced multidisciplinary IC design team developing next-generation semiconductor solutions. /p pThis is an opportunity to work somewhere that combines the technical challenges of advanced RD with the stability and long-term vision of an established organisation. /p p strong What you will be working on /strong /p p Lead top-level physical layout integration for advanced mixed-signal ASICs /p p Drive floorplanning, chip finishing and physical verification through to successful tape-out /p p Solve complex DRC/LVS/ERC challenges across advanced CMOS technologies /p p Collaborate closely with Analog, RF, Digital and System Designers /p p Contribute to ultra-low-power SoCs, imaging devices and advanced RF technologies /p p Help shape physical design methodologies and layout best practices /p p strong What we're looking for /strong /p p Strong experience delivering full-chip or top-level IC layout /p p Expertise with Cadence Virtuoso (Virtuoso XL) /p p Strong hands-on experience using Siemens Calibre (DRC/LVS/ERC) /p p Experience with mixed-signal, Analog and/or RF ASICs /p p Knowledge of advanced CMOS technologies /p p Proven experience supporting successful tape-outs /p p Experience resolving complex LVS issues and top-level integration is highly valued /p p Strong English communication skills /p pstrong Nice to have /strong /p p Ultra-Low Power (ULP) design /p p FinFET technologies /p p Advanced process nodes /p p ESD / Latch-up expertise /p p RF layout optimisation /p p strong Why consider this opportunity? /strong /p p Work on genuinely innovative semiconductor technology /p p Join an internationally recognised Swiss engineering organisation /p p Long-term permanent position /p p Collaborative, highly technical environment /p p Excellent work-life balance /p p Opportunity to influence future IC development /p p Relocation support available for suitable candidates /p