Senior IC Layout Engineer (F/M/D) 100%

ppbThe “Integrated and Wireless Systems” Business Unit, based in Neuchâtel, Switzerland is looking for a seasoned creative IC Layout Engineer. /b /p h3Your mission /h3 pYou will deliver high-quality IC layout solutions for advanced CMOS projects, with a strong emphasis on innovation and ultra-low-power designs. As part of an experienced layout team, you will lead top-level integration, verification, and documentation through to successful tape-out. You will work closely with Project Managers, IC designers, and PhD students on floor-planning and layout execution, including acceptance for fab integration. This role offers the chance to drive best-in-class IC designs and apply cutting-edge layout techniques and tools. /p h3Scope success criteria /h3 pYou own top-level integration layout deliverables (GDS, sign-off checks, and documentation) and support block-level work as needed; success is on-time, first-pass-quality tape-out readiness and smooth handoff for fab integration. /p h3Your responsibilities /h3 ul liExecute IC layout tasks (occasionally block-level; primarily top-level integration) through acceptance for integration and tape-out. /li liOwn chip finishing, verification, version control, documentation, and delivery flow. /li liMaster layout constraints and floor-planning for advanced CMOS designs. /li liApply best practices for ESD and latch-up, and for analog and RF layout. /li liRun LVS/DRC/ERC verification, troubleshoot and debug issues, and support tape-out execution. /li liParticipate actively in projects to ensure smooth IC layout execution (synchronization, tracking, guidelines, quality, etc.). /li liSupport project managers and designers in defining and executing layout tasks (preparation, resources, effort, and schedule). /li liMaintain IC layout expertise and state-of-the-art techniques (ULP SoC, imager, analog, and RF) for advanced CMOS nodes and foundries, including process features/options, tools, and IT flows. /li liEnsure work quality meets the company’s IC design and quality flow, and perform reviews/provide feedback. /li liSupport designers, partners, customers, and project managers on layout (e.g., Virtuoso) and physical verification tools (e.g., Calibre), and share methodology (matching, low‑power routing, RF parasitic avoidance, etc.). /li /ul h3Innovation /h3 ul liContribute to CSEM’s innovation efforts through layout execution, technology choices, and modern CAD techniques, with a focus on ultra-low-power ICs (ULP SoC, imager, analog, and RF). /li /ul h3Your profile /h3 h3Know-how /h3 ul li10+ years’ experience as an Analog/RF IC Layout Engineer (nanometer CMOS). /li liStrong experience with Cadence (e.g., Virtuoso) and Siemens verification tools (e.g., Calibre) in production flows. /li liStrong hands‑on layout experience leading top-level activities for mixed‑signal ASICs, from specifications and floor‑planning to submitting GDS to the foundry. /li liStrong experience with Cadence Virtuoso XL and Calibre DRC/LVS. /li liStrong understanding of the state‑of‑the‑art techniques, different circuit topologies and their constraints for the layout implementation. /li liEducation in Electronics (vocational training or university degree). /li /ul h3Interpersonal skills /h3 ul liCurious, autonomous, and hands‑on. /li liYou are motivated to play a key role in developing innovative solutions and can adapt to new situations. /li liYou are a good team player with strong communication skills in English; French or German is an asset. /li /ul pWe are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity. /p /p #J-18808-Ljbffr